Recently, the ATM communication is noticed as a new communication method for the multimedia age. In the conventional STM communication method, during communication, the physical circuit of the STM network is always occupied in every media between terminals, but in the ATM communication system, the circuit between terminals is set as a logic virtual path, and the physical circuit is occupied dynamically only by the necessary portion depending on the necessity, so that an efficient multimedia communication is realized.
FIG. 26 shows a configuration of a system for transmitting and receiving data on the STM circuit through the ATM network by using a conventional cell assembly and disassembly device (cell disassembly device). Reference numerals 61a, 61b, and 61c denote conventional cell assembly and disassembly devices which can transmit and receive the effective data on the STM circuit by transforming into ATM cells (hereinafter called cells), reference numeral 63 denotes an ATM network for communication in asynchronous transfer mode, 62a, 62b, and 62c denote STM circuit interfaces, reference numerals 64a, 64b, and 64c denote ATM circuit interfaces, and reference numerals 65a and 65b denote virtual paths set on the ATM network 63.
In the STM/ATM communication system having such configuration, effective data (continuous data) for the STM circuit interface 62b entered in the cell assembly and disassembly device 61a from the STM circuit interface 62a is sequentially assembled into a cell, which is a 53-byte fixed length packet, in the cell assembly and disassembly device 61a, and is provided with VPI (virtual path identifier) #1 in the header, and is transmitted to the ATM network 63 at a specific speed. Consequently, the cell transferred on the virtual path 65a according to VPI#1 is received in the cell assembly and disassembly device 61b, and is returned from the cell into the original continuous data herein, and is transmitted to the STM circuit interface 62b. 
Similarly, as a flow in reverse direction, effective data for the STM circuit interface 62a entered in the cell assembly and disassembly device 61b from the STM circuit interface 62b is sequentially assembled into a cell in the cell assembly and disassembly device 61b, and is provided with VPI#1 in the header, and is transmitted to the ATM network 63 at a specific speed. Consequently, the cell transferred on the virtual path 65a according to VPI#1 is received in the cell assembly and disassembly device 61a, and is returned into the original continuous data herein, and is transmitted to the STM circuit interface 62a. 
On the other hand, effective data (continuous data) for the STM circuit interface 62c entered in the cell assembly and disassembly device 61a from the STM circuit interface 62a is sequentially assembled into a cell in the cell assembly and disassembly device 61a, and is provided with VPI#2 in the header, and is transmitted to the ATM network 63 at a specific speed. Consequently, the cell transferred on the virtual path 65b according to VPI#2 is received in the cell assembly and disassembly device 61c, and is returned from the cell into the original continuous data herein, and is transmitted to the STM circuit interface 62c. 
Similarly, as a flow in reverse direction, effective data for the STM circuit interface 62a entered in the cell assembly and disassembly device 61c from the STM circuit interface 62c is sequentially assembled into a cell in the cell assembly and disassembly device 61c, and is provided with VpI#2 in the header, and is transmitted to the ATM network 63 at a specific speed. Consequently, the cell transferred on the virtual path 65b according to VPI#2 is received in the cell assembly and disassembly device 61a, and is returned into the original continuous data herein, and is transmitted to the STM circuit interface 62a. 
The cell assembly and disassembly device 61 (cell assembly and disassembly device 61a, 61b, or 61c) has a structure as shown in a functional block diagram in FIG. 27. The cell assembly and disassembly device 61 comprises the ATM circuit interface unit 71 for terminating the ATM circuit interface (physical layer processing), the cell assembly unit 73 for forming the continuous data received from STM circuit interface unit 72 into a cell, the cell disassembly unit 74 ford is assembling the cell received from the ATM circuit interface unit 71 to restore into continuous data, the STM circuit interface 72 for terminating the STM circuit interface, and the device management unit 75 for managing the entire devices of the cell assembly and disassembly device 61. The ATM circuit interface 64 may be any one of the ATM circuit interfaces 64a, 64b, and 64c, and the STM circuit interface 62 may be any one of the STM circuit interfaces 62a, 62b, and 62c. 
According to the ITU-T, in the ITU-T Recommendation I.363.1, the structured data transfer method is designated as the cell transfer method of data on the STM circuit having a specific frame period through the ATM network 63. A cell format used in the conventional structured data transfer method is shown in FIG. 21. The cell assembly unit 73 divides only the effective data extracted from arbitrary plural time slots, out of the STM circuit interface 62 composed of [64 kb/s]×n (n: natural number) time slots (TS), in the unit of 46 bytes (in the case of P format) or 47 bytes (in the case of non-P format), adds AAL1 (ATM adaptation layer type 1) header and ATM header (including VPI), assembles the cell in the format shown in FIG. 28 by destination (virtual path 65), and transmits to the ATM circuit interface unit 71. The virtual path 65 is either virtual path 65a or virtual path 65b. 
On the other hand, the cell disassembly unit 74 analyzes the VPI in the header of the cell received from the ATM circuit interface unit 71, judges the sender (virtual path 65), analyzes the sequence number in the AAL1 header, detects cell discarding and insertion of wrong cell, and processes countermeasures, absorbs delay fluctuations occurring during cell transfer in the ATM network 63 in every virtual path 65, distributes the data extracted from the payload into necessary time slots according to the sender, and transmits to the STM circuit interface unit 72. Further, the cell disassembly unit 74, when receiving a cell in P format, analyzes the pointer field, detects the boundary of frame period in the STM circuit, and determines assignment of which byte of the data extracted from the payload in which time slot.
The cell disassembly unit 74 has a structure as shown in a functional block diagram in FIG. 29. The cell disassembly unit 74 comprises following units. The AAL1 processor 81 for extracting the VPI and data (including frame boundary information) from the received cell, and transmitting respectively to a write controller 83 and the fluctuation absorption buffer unit 82. The fluctuation absorption buffer unit 82 for temporarily storing the data extracted from the payload of the received cell together with the frame boundary information directly in every virtual path 65 (VPI), and absorbing the delay fluctuation occurring during cell transfer in the ATM network 63. The write controller 83 for analyzing the received VPI, judging the sender (virtual path 65), and generating a write signal to the fluctuation absorption buffer unit 82 on the basis thereof. The buffer monitor unit 84 for monitoring the data accumulated amount in the fluctuation absorption buffer unit 82 in every virtual path 65 (VPI), and controlling the operation of the write controller 83 and read controller 85 on the basis thereof. The read controller 85 for reading out the data from the fluctuation absorption buffer unit 82 according to the timing information from the STM circuit interface unit 72 and distributing into necessary time slots. The VP/TS conversion table 86 for storing the corresponding relation of the virtual path 65 and distribution time slots, and noticing to the read controller 85.
The fluctuation absorption buffer 82 has a structure as shown in a functional block diagram in FIG. 30. The fluctuation absorption buffer 82 comprises following units. The separator 91 for distributing the write data and frame boundary information from the AAL1 processor 81 into individual buffers VPB1 (VPI#1) to VPBm (VPI#m) in a cell buffer 92 according to the instruction (write signal) from the write controller 83. The cell buffer 92 for storing the write data and frame boundary information temporarily in each virtual path 65 (VPI). The multiplexer 93 for multiplexing the data and frame boundary information being red out from the individual buffer VPB1 to VPBm in the cell buffer 92 according to the instruction (read signal) from the read controller 85. VPTH1 to VPTHm are the reading-start thresholds set respectively in the buffer VPB1 to VPBm. Although VPTH1 to VPTHm are shown in FIG. 30, they will utilized in the explanation of operation provided later. These thresholds are actually stored in the buffer monitor unit 84.
The device management unit 75 shown in FIG. 27 manages the entire structure of the cell assembly and disassembly device 61, and sets necessary parameters and collects status in the individual units of the cell disassembly unit 74, ATM circuit interface unit 71, cell assembly unit 73, and STM circuit interface unit 72. To realize this function, the device management unit 75 and individual units are connected through a control bus. For the sake of simplicity of the functional block diagram, the control bus is show in FIG. 27 only, but for setting of parameters and collection of status, sub-blocks in individual units shown in FIG. 27, for example, sub-blocks in the cell disassembly unit 74 are also connected with control bus.
Further, the data bus width in the ATM circuit interface unit 64 and STM circuit interface unit 62 is serial (1 bit), but in the cell assembly and disassembly device 61, generally, data is exchanged in the width of 8 bits. For example, when the ATM interface speed is 155.52 MHz, inside the cell assembly and disassembly device 61, as mentioned above, the interface is 8-bit wide, and most of the parts operate in the clock of the ATM interface system, and therefore the internal basic clock is 19.44 MHz (=155.52 MHz/8 bits).
The operation of the conventional cell assembly and disassembly device 61 will now be explained. The STM circuit interface 72 shown in FIG. 27 converts the bit row received from the STM circuit interface 62 from serial to parallel (8 bits), extracts the frame boundary and time slot, and transmits all data, together with the timing information, to the cell assembly unit 73. The cell assembly unit 73 assembles only the effective data in a cell of a format shown in FIG. 28 in every destination (virtual path 65) according to the instruction (to assign the data from which time slot into which virtual path 65) from a TS/VP conversion table not shown in the diagram, and transmits to the ATM circuit interface unit 71. The ATM circuit interface unit 71 inserts the cell received from the cell assembly unit 73 into the payload of physical layer frame such as SDH (synchronous digital hierarchy) or SONET (synchronous optical network), converts from parallel to serial, and transmits to the ATM circuit interface 64.
Similarly, as a flow in reverse direction, the ATM circuit interface unit 71 converts the bit row received from the ATM circuit interface 64 from serial to parallel, processes the physical layer by detecting cell synchronism or the like, and transmits all effective extracted cells together with timing information to the cell disassembly unit 74.
The AAL1 processor 81 in the cell disassembly unit 74 shown in FIG. 29 extracts the VPI from the header of the received cell, notices it to the write controller 83, and analyzes the sequence number in the AAL1 header, and detects cell discarding and insertion of wrong cell. When cell discarding is detected, in this case, the lost data is compensated (inserting all-1 pattern of 46 bytes if the discarded cell is supposed to be P format, or 47 bytes in the case of non-P format), and further when the discarded cell is supposed to be P format, the frame boundary information is also predicted and compensated. When a wrong cell insertion is detected, the wrong inserted cell is discarded. Later, the information extracted from the payload of the received cell and frame boundary information are transmitted to the fluctuation absorption buffer unit 82.
The write controller 83 analyzes the VPI received from the AAL1 processor 81, judges the sender (virtual path 65), generates a corresponding write signal, and transmits to the fluctuation absorption buffer unit 82 and buffer monitor unit 84. In FIG. 30, the fluctuation absorption buffer unit 82 stores, according to the write signal received from the write controller 83, the data and frame boundary information received from the AAL1 processor 81 temporarily in the individual buffers VPB1 to VPBm prepared in each virtual path 65 (VPI#1 to #m).
The buffer monitor unit 84 monitors the data accumulated amount held in the cell buffer 92 in every individual buffers VPB1 to VPBm, from the write signal from the write controller 83 and read signal from the read controller 85, and controls the operation of the write controller 83 and read controller 85 according to the result. For example, the data accumulating amount in the individual buffers VPB1 to VPBm which are empty upon start of communication gradually increases by turning on the write action instruction and turning off the read action instruction until reaching the reading-start thresholds VPTH1 to VPTHm by write action, and when the data accumulated amount reaches the reading-start thresholds VPTH1 to VPTHm, the read action instruction is also turned on sequentially.
The read controller 85, when the reading-start instruction from the buffer monitor unit 84 is ON, generates read signals to be distributed correctly into the time slots in which read data is distributed, and transmits to the fluctuation absorption buffer unit 82, according to the instruction (to assign the data from which virtual path 65 into which time slot time slot) from the VP/TS conversion table 86, frame boundary information from the fluctuation absorption buffer 82, and timing information from the STM circuit interface unit 72.
The VP/TS conversion table 86 stores the corresponding relation of the virtual path 65 (VPI) and time slot, that is, the information showing which virtual path 65 is set (which VPI is present), and which time slot is used by each virtual path 65, and notices the information to the read controller 85. The STM circuit interface unit 72 inserts the data being readout by the read controller 85 into the payload (time slot) of the physical layer frame, converts from parallel into serial, and transmits to the STM circuit interface 62.
Thus, in the conventional method, the received data and frame boundary information are once held in the cell buffer 92 in the fluctuation absorption buffer 82, and by stopping the reading action (delaying the reading-start timing) until the data accumulated amount reaches the reading-start threshold after start of communication, delay fluctuations occurring during cell transfer in the ATM network 63 is absorbed, and the continuity of the data issued to the STM circuit interface 62 is assured.
Herein, the reading-start thresholds VPTH1 to VPTHm of individual buffers VPB1 to VPBm can be basically expressed with the following equation (1), supposing the maximum of the delay fluctuation determined as the characteristic of the ATM network 63 to be ±D and the communication speed of the virtual path 65 accommodated to be V (identifier k=1 to m).VPTHk=Vk×D  (1)
The capacity Lk (identifier k=1 to m) required as individual buffers VPB1 to VPBm can be basically expressed with the following equation (2).Lk=2×VPTHk=2XVk×D  (2)
However, since the received data is written into the cell buffer 82 in cell unit, if the calculation result in equation 1 is 47 bytes (worth 1 cell) or less, it is general to express as follows.VPTHk=48 bytes (1 cell+1 byte)  (3)Lk=94 bytes (2 cells)  (4)
As shown in equation (2), the capacity L (capacity L1 to Lm) of individual buffers VPB1 to VPBm used as fluctuation absorption buffers basically depends on the communication speed of the virtual buffer accommodated. Accordingly, in the conventional cell assembly and disassembly device 61, the cell buffer 92 is realized mainly by the following two methods, that is, the individual memory method and common memory method.
In the individual memory method, one memory is divided into plural fixed banks, and the banks are used as individual buffers VPB1 to VPBm, or plural individual memories are prepared physically, and used as individual buffers VPB1 to VPBm.
In this method, since the individual buffers VPB1 to VPBm are composed of simple first-in first-out (FIFO) memories, the memory control circuit is simple. However, so as to be flexibly applicable to completely different communication speeds in individual virtual paths 65, capacities of all individual buffers VPB1 to VPBm must conform to the maximum communication speed of the STM circuit interface 62, for example, in the case of the ISDN (integrated services digital network) temporary group speed interface, the capacity must be large enough to accommodate the speed of 1.536 Mb/s, and this is the simplest configuration and the memory control circuit is the easiest, but the total memory capacity becomes extremely large.
Accordingly, it has been attempted to curtail the total memory capacity by providing the applicable communication speed with limiting conditions and making use of the regularity of the communication speeds in the limiting conditions. For example, in the limiting conditions “to be applicable to maximum speed and communication speed to the power of 2 of 64 kb/s only,” the memory capacity of individual buffers VPB1 to VPBm is composed of 1 for 1.536 Mb/s+2 for 512 kb/s+3 for 256 kb/s+6 for 128 kb/s+12 for 64 kb/s. In spite of such curtailing means, however, the cell buffer 92 cannot be realized at the minimum memory cost in this method. Features of this method are briefly summarized as follows.
Merit: Memory control circuit is simple.
Demerit: Total memory capacity is very large.
On the other hand, in the common memory method, one memory is finely divided into cell levels (for example, in the units of 64 bytes each), and obtained memory blocks are commonly shared by all virtual paths 65, and in each virtual path 65 as required, plural memory blocks are occupied sequentially, and combined in chain, so that the individual buffers VPB1 to VPBm are realized.
This method is flexibly applicable to various communication speeds, and requires only a minimum limit of total memory capacity because the memory is shared, but the demerit is that the memory control circuit is very complicated as disclosed, for example, in Japanese Laid-open Patent No. 8-331149. The total memory capacity (common memory capacity) Ls required in this method may be basically expressed with the following equation (5), supposing the maximum communication speed of the STM circuit interface 62 to be Vmax.Ls=2×Vmax×D  (5)
Features of this method are briefly summarized as follows.
Merit: Total memory capacity is small.
Demerit: Memory control circuit is extremely complicated.
According to the prior art, however, since fluctuations are absorbed by the buffer of which capacity depends on the virtual path which is variable in communication speed, if attempted to curtail the total capacity of the memory for absorbing fluctuations, the memory control circuit is complicated and the cost is increased, or if attempted to simplify the memory control circuit, the total capacity of the memory for absorbing fluctuations becomes large, and the cost is increased, too.
It is an object of this invention to provide a cell disassembly device capable of suppressing both increase of total capacity of cell for absorbing fluctuations and complication of memory control circuit. It is also an object of this invention to provide a cell disassembly method and a computer-readable recording medium which records a computer program that realizes the method according to this invention on a computer.